The present invention relates generally to semiconductors and more specifically to etch stop layers in semiconductor processing.
In the manufacture of integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This interconnection process is generally called xe2x80x9cmetallizationxe2x80x9d, and is performed using a number of different photolithographic and deposition techniques.
In one interconnection process, which is called a xe2x80x9csingle inlaidxe2x80x9d technique, channels of conductor material are deposited in a channel dielectric layer. The process starts with the placement of a first channel etch stop layer and a first channel dielectric layer, which are respectively a nitride and an oxide layer, over the semiconductor devices. A first inlaid step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The inlaid step photoresist is stripped and an optional thin adhesion layer is deposited to coat the walls of the first channel opening to ensure good adhesion and electrical contact of subsequent layers to the underlying semiconductor devices. A barrier layer is then deposited on the adhesion layer improve the formation of subsequently deposited conductor material and to act as a barrier material to prevent diffusion of such conductor material into the oxide layer and the semiconductor devices. A first conductor material is then deposited and subjected to a chemical-mechanical polishing process which removes the first conductor material above the first channel oxide layer and inlays the first conductor material in the first channel openings to form the first channels.
In another interconnection process, which is called a xe2x80x9cdual inlaidxe2x80x9d technique, vias and channels are formed at the same time. The via formation step of the dual inlaid process starts with the deposition of a thin etch stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate via areas over the first channels.
A nitride etch is then used to etch out the via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second inlaid step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The inlaid photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. An adhesion layer is often deposited to coat the via openings and the second channel openings. Next, a barrier layer is deposited on the adhesion layer, and the two layers are collectively referred to as the barrier layer. This is followed by a deposition of the second conductor material in the second channel openings and the via openings to form the second channel and the via. A second chemical mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by vias.
The use of the single and dual inlaid techniques eliminate metal etch and dielectric gap fill steps typically used in the metallization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metallization materials, such as copper, which are very difficult to etch.
One drawback of using copper as the conductor material is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through inter layer dielectric materials, such as silicon oxide. When copper diffuses through interlayer dielectric layers, it can cause leakage to neighboring interconnect lines on the semiconductor substrate. To prevent diffusion, highly diffusion resistive barrier materials, such as titanium, tantalum, tungsten, their nitrides, and combinations thereof, are used as barrier materials.
After deposition of the barrier layer, a seed layer of conductor material, such as copper, is deposited by an ion metal plasma (IMP) deposition, chemical vapor deposition (CVD), or an electroless plating process. This seed layer is subsequently used as one electrode in an electroplating process which deposits the conductor material which completely fills the channels and vias.
With the development of high integration and high-density very large scale integrated circuits, reductions in the size of transistors and interconnects has been accompanied by increases in switching speed of such integrated circuits. The closeness of the interconnects and the switching speeds have increased the problems due to switching slow-downs resulting from capacitance coupling effects between the closely positioned, parallel conductive channels connecting high switching speed semiconductor devices in these integrated circuits. Since the capacitance coupling effects are reduced when the dielectric constant of the material between the channels is reduced, this has rendered current silicon nitride, which has a dielectric constant in excess of 7.5, problematic for protective dielectric layers.
A solution for reducing the dielectric constant of the materials used in interconnects has been long sought but has eluded those skilled in the art. In this area, even small reductions in the dielectric constant are significant.
The present invention provides an integrated circuit having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a barrier layer lining the channel opening, and a conductor core filling the channel opening. A via stop layer is formed over the channel dielectric layer to have low quantities of hydrogen below 15 atomic % and a via dielectric layer is formed over the via stop layer and has a via opening. A second channel dielectric layer over the via dielectric layer has a second channel opening. A second conductor core, filling the second channel opening and the via opening, is connected to the semiconductor device. The via stop layer halves the capacitive coupling between the channels compared to prior art via stop layers.
The present invention further provides a method for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer is formed on the device dielectric layer. A channel opening is formed in the channel dielectric layer, and a barrier layer is deposited to line the channel opening. A conductor core is deposited to fill the channel opening. A via stop layer is deposited by a non-hydrogen containing plasma deposition process over the channel dielectric layer to have low quantities of hydrogen below 15 atomic % and a via dielectric layer is formed over the via stop layer and has a via opening. A second channel dielectric layer over the via dielectric layer has a second channel opening. A second conductor core filling the second channel opening and the via opening is connected to the semiconductor device. The via stop layer halves the capacitive coupling between the channels compared to prior art via stop layers.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.